GPIO Intel® FPGA IP User Guide

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Intel® Arria® 10 ndi Intel® Cyclone® 10 GX Devices

Zasinthidwa kwa Intel® Quartus® Prime Design Suite: 21.2
Mtundu wa IP: 20.0.0

Baibulo Lomasulira                                                               ID: 683136
Tumizani Ndemanga             ug-altera_gpio            Mtundu: 2021.07.15

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GPIO Intel® FPGA IP core imathandizira cholinga cha I/O (GPIO) ndi zigawo zake. Mutha kugwiritsa ntchito ma GPIO pamapulogalamu onse omwe sali achindunji kwa ma transceivers, malo okumbukira, kapena LVDS.

GPIO IP Core ikupezeka pazida za Intel Arria® 10 ndi Intel Cyclone® 10 GX zokha. Ngati mukusamuka kuchokera ku zida za Stratix® V, Arria V, kapena Cyclone V, muyenera kusamutsa ma cores a ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, kapena ALTIOBUF IP.

Zambiri Zogwirizana

• IP Migration Flow ya Arria V, Cyclone V, ndi Stratix V Devices patsamba 22
• Intel Stratix 10 I/O Maupangiri Othandizira
  Imapereka chiwongolero cha GPIOIP pazida za Intel Stratix 10.
• Chiyambi cha Intel FPGA IP Cores
  Amapereka zambiri za Intel FPGA IP cores, kuphatikiza parameterizing, kupanga, kukweza, ndi kuyerekezera ma IP cores.
• Kupanga Version-Independent IP ndi Qsys Simulation Scripts
  Pangani zolemba zofananira zomwe sizikufuna kusinthidwa pamanja pamapulogalamu kapena kukweza mtundu wa IP.
• Ntchito Zabwino Kwambiri Zoyang'anira Ntchito
  Malangizo oyendetsera bwino komanso kusuntha kwa polojekiti yanu ndi IP files.
• GPIO Intel FPGA IP User Guide Archives patsamba 24
  Imapereka mndandanda wazowongolera zamagwiritsidwe akale a GPIO IP core.
• Double Data Rate I/O (ALTDDIO_IN, ALTDDIO_OUT, ndi ALTDDIO_BIDIR) IP Cores User Guide
• I/O Buffer (ALTIOBUF) IP Core User Guide

Zambiri Zotulutsidwa za GPIO Intel FPGA IP

Mitundu ya Intel FPGA IP imafanana ndi mitundu ya Intel Quartus® Prime Design Suite mpaka v19.1. Kuyambira mu Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP ili ndi ndondomeko yatsopano yomasulira.

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Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa cha kugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito. *Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

ISO 9001:2015 Adalembetsedwa

Nambala ya Intel FPGA IP (XYZ) imatha kusintha ndi mtundu uliwonse wa pulogalamu ya Intel Quartus Prime. Kusintha kwa:

• X ikuwonetsa kukonzanso kwakukulu kwa IP. Mukasintha pulogalamu ya Intel Quartus Prime, muyenera kukonzanso IP.
• Y akuwonetsa kuti IP ili ndi zatsopano. Panganinso IP yanu kuti muphatikizepo zatsopanozi.
• Z ikuwonetsa kuti IP imaphatikizapo zosintha zazing'ono. Panganinso IP yanu kuti ikhale ndi zosinthazi.

Table 1. GPIO Intel FPGA IP Core Current Release Information

Kanthu	Kufotokozera
Mtundu wa IP	20.0.0
Intel Quartus Prime Version	21.2
Tsiku lotulutsa	2021.06.23

GPIO Intel FPGA IP Features

GPIO IP pachimake imaphatikizapo zinthu zothandizira zida za I/O za chipangizocho. Mutha kugwiritsa ntchito Intel Quartus Prime parameter editor kukonza GPIO IP core.

GPIO IP pachimake imapereka zigawo izi:

• Kutulutsa kwa data kuwirikiza kawiri (DDIO)—chigawo cha digito chomwe chimachulukitsa kapena kuchepetsa kuchuluka kwa data panjira yolumikizirana.
• Unyolo wochedwetsa - konzani maunyolo ochedwa kuti achedwetse ndikuthandiza kutseka kwa nthawi ya I/O.
• Ma buffer a I/O-alumikizani mapepala ku FPGA.

GPIO Intel FPGA IP Data Njira

Chithunzi 1. High-Level View ya GPIO Yokhayokha

Table 2. GPIO IP Core Data Path Modes

Njira ya Data	Register Mode
	Kulambalala	Register yosavuta	DDR I/O
			Mtengo Wonse	Theka la Mtengo
Zolowetsa	Deta imachoka pakuchedwa kupita pachimake, ndikudutsa ma I/O onse awiri (DDIOs).	DDIO yanthawi zonse imagwira ntchito ngati kaundula wosavuta, kumadutsa ma DDIO apakati. The Fitter amasankha kulongedza kaundula mu I/O kapena kukhazikitsa kaundula pachimake, malinga ndi dera ndi nthawi malonda malonda.	DDIO yathunthu imagwira ntchito ngati DDIO wamba, kudutsa ma DDIO apakati.	DDIO yathunthu imagwira ntchito ngati DDIO wamba. Ma DDIO okhala ndi theka amasintha deta yonse kukhala ya theka.
Zotulutsa	Deta imachoka pachimake molunjika kupita kumalo ochedwa, kudutsa ma DDIO onse.	DDIO yanthawi zonse imagwira ntchito ngati kaundula wosavuta, kumadutsa ma DDIO apakati. The Fitter amasankha kulongedza kaundula mu I/O kapena kukhazikitsa kaundula pachimake, malinga ndi dera ndi nthawi malonda malonda.	DDIO yathunthu imagwira ntchito ngati DDIO wamba, kudutsa ma DDIO apakati.	DDIO yathunthu imagwira ntchito ngati DDIO wamba. Ma DDIO okhala ndi theka amasintha deta yonse kukhala ya theka.
Bilida	Buffer yotulutsa imayendetsa pini yotulutsa ndi buffer yolowera.	DDIO yathunthu imagwira ntchito ngati kaundula wosavuta. Buffer yotulutsa imayendetsa pini yotulutsa ndi buffer yolowera.	DDIO yathunthu imagwira ntchito ngati DDIO wamba. Buffer yotulutsa imayendetsa pini yotulutsa ndi buffer yolowera. Buffer yolowetsa imayendetsa seti ya ma flip-flops atatu.	DDIO yathunthu imagwira ntchito ngati DDIO wamba. Ma DDIO a theka amasintha deta yathunthu kukhala theka. Buffer yotulutsa imayendetsa pini yotulutsa ndi buffer yolowera. Buffer yolowetsa imayendetsa seti ya ma flip-flops atatu.

Ngati mugwiritsa ntchito ma asynchronous omveka bwino komanso okonzedweratu, ma DDIO onse amagawana zizindikiro zomwezi.

Ma DDIO okwera theka komanso athunthu amalumikizana ndi mawotchi osiyana. Mukamagwiritsa ntchito ma DDIO apakati komanso athunthu, wotchi yanthawi zonse iyenera kuthamanga kuwirikiza kawiri kuchuluka kwa theka. Mutha kugwiritsa ntchito maulalo osiyanasiyana kuti mukwaniritse zofunikira zanthawi.

Zambiri Zogwirizana
Mabasi Olowetsa ndi Kutuluka Mabasi Okwera ndi Otsika patsamba 12

Njira Yolowetsa

Pad imatumiza deta ku bafa yolowetsa, ndipo cholowacho chimadyetsa chinthu chochedwa. Deta ikapita ku zomwe zachedwetsa, ma programmable bypass multiplexers amasankha mawonekedwe ndi njira zogwiritsira ntchito. Njira iliyonse yolowetsa ili ndi ma s awiri.tagma DDIO, omwe ali odzaza ndi theka.

Chithunzi 2. Chosavuta View ya Njira Yolowera Imodzi ya GPIO

1. Pad imalandira deta.
2. DDIO IN (1) imajambula deta yokwera ndi kutsika m'mphepete mwa ck_fr ndikutumiza deta, zizindikiro (A) ndi (B) mu chithunzi chotsatirachi, pa mlingo umodzi wa deta.
3. DDIO IN (2) ndi DDIO IN (3) amachepetsa chiwerengero cha deta.
4. dout[3:0] ikupereka deta ngati basi yapakati.

Chithunzi 3. Njira Yolowetsa Waveform mu DDIO Mode yokhala ndi Half-Rate Conversion

M'chiwerengerochi, deta imachokera ku wotchi yathunthu pawiri deta mpaka theka la wotchi pa mlingo umodzi wa data. Chiwerengero cha deta chimagawidwa ndi zinayi ndipo kukula kwa basi kumawonjezeka ndi chiwerengero chomwecho. Kutulutsa konse kudzera pa GPIO IP pachimake sikunasinthe.

Ubale weniweni wa nthawi pakati pa ma siginecha osiyanasiyana utha kusiyanasiyana kutengera kapangidwe kake, kuchedwa, ndi magawo omwe mumasankha mawotchi anthawi zonse ndi theka.

Zindikirani: GPIO IP pachimake sichigwirizana ndi kusintha kwamphamvu kwa ma pin bidirectional. Pamapulogalamu omwe amafunikira kusanja kosinthika kwa ma pin obwereza, onaninso zokhudzana ndi izi.

Zambiri Zogwirizana

• PHY Lite for Parallel Interfaces Intel FPGA IP Core User Guide: Intel Stratix 10, Intel Arria 10, ndi Intel Cyclone 10 GX Devices
  Imapereka zambiri zamapulogalamu omwe amafunikira OCT yamphamvu pamapini obwereza.
• Zotuluka ndi Zotuluka Zimathandizira Njira patsamba 7

Kutulutsa ndi Kutulutsa Zimathandizira Njira

Zomwe zimachedwa kutulutsa zimatumiza deta ku pad kudzera mu buffer yotulutsa.

Njira iliyonse yotulutsa imakhala ndi ma s awiritagma DDIOs, omwe ndi theka komanso kuchuluka kwathunthu.

Chithunzi 4. Chosavuta View ya Njira Yotulutsa Imodzi ya GPIO

Chithunzi 5. Njira Yotulutsa Waveform mu DDIO Mode yokhala ndi Half-Rate Conversion

Chithunzi 6. Chosavuta View ya Output Yambitsani Njira

Kusiyana pakati pa njira yotulutsa ndi njira yotulutsa (OE) ndikuti njira ya OE ilibe DDIO yathunthu. Kuti muthandizire kukhazikitsidwa kwa zolembetsa zodzaza munjira ya OE, kaundula wosavuta amagwira ntchito ngati DDIO yathunthu. Pachifukwa chomwecho, DDIO imodzi yokha ya theka ndiyo ilipo.

Njira ya OE imagwira ntchito m'njira zitatu zotsatirazi:

• Bypass-pachimake chimatumiza deta molunjika kumalo ochedwa, kudutsa ma DDIO onse.
• Kaundula Yopakidwa - imadutsa theka la DDIO.
• Kutulutsa kwa SDR pa theka la theka - ma DDIO a theka amasintha deta kuchokera pamlingo wathunthu mpaka theka.

Zindikirani: GPIO IP pachimake sichigwirizana ndi kusintha kwamphamvu kwa ma pin bidirectional. Pamapulogalamu omwe amafunikira kusanja kosinthika kwa ma pin obwereza, onaninso zokhudzana ndi izi.

Zambiri Zogwirizana

• PHY Lite for Parallel Interfaces Intel FPGA IP Core User Guide: Intel Stratix 10, Intel Arria 10, ndi Intel Cyclone 10 GX Devices
  Imapereka zambiri zamapulogalamu omwe amafunikira OCT yamphamvu pamapini obwereza.
• Njira yolowera patsamba 5

GPIO Intel FPGA IP Interface Signals

Kutengera makonda omwe mumatchula, ma signature osiyanasiyana akupezeka pa GPIO IP pachimake.

Chithunzi 7. GPIO IP Core Interfaces

Chithunzi 8. GPIO Interface Signals

Table 3. Pad Interface Signals

Mawonekedwe a pad ndi kulumikizana kwakuthupi kuchokera pa GPIO IP pachimake kupita pa pad. Mawonekedwewa amatha kukhala olowera, otulutsa kapena mawonekedwe awiri, kutengera kasinthidwe ka IP. Patebuloli, SIZE ndiye kukula kwa data komwe kumatchulidwa mu IP core parameter editor.

Dzina la Signal	Mayendedwe	Kufotokozera
pad_mu[SIZE-1:0]	Zolowetsa	Lowetsani chizindikiro kuchokera pa pad.
pad_mu_b[SIZE-1:0]	Zolowetsa	Node yolakwika ya chizindikiro cholowetsa chosiyana kuchokera pa pad. Doko ili likupezeka ngati muyatsa Gwiritsani ntchito buffer yosiyana mwina.
pad_out[SIZE-1:0]	Zotulutsa	Chizindikiro chotuluka ku pad.
pad_out_b[SIZE-1:0]	Zotulutsa	Negative node ya masiyanidwe otulutsa chizindikiro ku pad. Doko ili likupezeka ngati muyatsa Gwiritsani ntchito buffer yosiyana mwina.
pad_io[SIZE-1:0]	Bilida	Kulumikizana kwa siginecha ya Bidirectional ndi pad.
pad_io_b[SIZE-1:0]	Bilida	Node yolakwika yolumikizana ndi ma siginali yosiyana ndi pad. Doko ili likupezeka ngati muyatsa Gwiritsani ntchito buffer yosiyana mwina.

Table 4. Zizindikiro za Chiyankhulo cha Data

Mawonekedwe a data ndi njira yolowera kapena yotulutsa kuchokera pachimake cha GPIO IP kupita pachimake cha FPGA. Patebuloli, SIZE ndiye kukula kwa data komwe kumatchulidwa mu IP core parameter editor.

Dzina la Signal	Mayendedwe	Kufotokozera
din[DATA_SIZE-1:0]	Zolowetsa	Kuyika kwa data kuchokera pachimake cha FPGA pazotulutsa kapena njira ziwiri. DATA_SIZE zimatengera kalembera: Kulambalala kapena kaundula wamba—DATA_SIZE = SIZE DDIO yopanda malire—DATA_SIZE = 2 × SIZE DDIO yokhala ndi malingaliro ofika theka—DATA_SIZE = 4 × SIZE
kudandaula[DATA_SIZE-1:0]	Zotulutsa	Kutulutsa kwa data pachimake cha FPGA pakulowetsa kapena kutsata njira ziwiri, DATA_SIZE zimatengera kalembera: Kulambalala kapena kaundula wamba—DATA_SIZE = SIZE DDIO yopanda malire—DATA_SIZE = 2 × SIZE DDIO yokhala ndi malingaliro ofika theka—DATA_SIZE = 4 × SIZE
uwu[OE_SIZE-1:0]	Zolowetsa	Kulowetsa kwa OE kuchokera pachimake cha FPGA mumayendedwe otulutsa ndi Yambitsani kutulutsa koyambitsa port kuyatsa, kapena njira ziwiri. OE ndi yogwira ntchito. Mukatumiza deta, ikani chizindikirochi kukhala 1. Mukalandira deta, ikani chizindikirochi kukhala 0. OE_SIZE zimatengera kalembedwe kake: Kulambalala kapena kaundula wamba—DATA_SIZE = SIZE DDIO yopanda malire a theka—DATA_SIZE = SIZE DDIO yokhala ndi malingaliro ofika theka—DATA_SIZE = 2 × SIZE

Table 5. Zizindikiro za Chiyankhulo cha Clock

Mawonekedwe a wotchi ndi mawonekedwe a wotchi yolowera. Zimakhala ndi zizindikiro zosiyanasiyana, kutengera kasinthidwe. GPIO IP Core imatha kukhala ndi ziro, imodzi, ziwiri, kapena zolowetsa mawotchi anayi. Mawotchi a wotchi amawonekera mosiyana m'masinthidwe osiyanasiyana kuti awonetse ntchito yeniyeni yochitidwa ndi chizindikiro cha wotchi.

Dzina la Signal	Mayendedwe	Kufotokozera
ck	Zolowetsa	Munjira zolowera ndi zotulutsa, wotchi iyi imadyetsa zolembera zodzaza kapena DDIO ngati muyimitsa Hafu Rate logic parameter. Munjira ya bidirectional, wotchi iyi ndi wotchi yapadera yolowera ndi njira zotuluka ngati muyimitsa Olekanitsa mawotchi olowetsa/otulutsa parameter.
ck_fr	Zolowetsa	Munjira zolowetsa ndi zotulutsa, mawotchiwa amadyetsa ma DDIO amtundu wonse ndi theka ngati muyatsa Hafu Rate logic parameter. Mumayendedwe apawiri, njira zolowera ndi zotulutsa zimagwiritsa ntchito mawotchi awa ngati mutseka Olekanitsa mawotchi olowetsa/otulutsa parameter.
ck_hr
ck_mu	Zolowetsa	Mumayendedwe apawiri, mawotchiwa amadyetsa zolembera zodzaza kapena DDIO m'njira zolowera ndi zotuluka ngati mufotokoza zonse ziwiri izi: Zimitsani Hafu Rate logic parameter. Yatsani Olekanitsa mawotchi olowetsa/otulutsa parameter.
ck_ku
ck_fr_mu	Zolowetsa	Mumayendedwe apawiri, mawotchiwa amadyetsa DDIOS yathunthu ndi theka munjira zolowera ndi zotuluka ngati mufotokoza zonse ziwirizi. Yatsani Hafu Rate logic parameter. Yatsani Olekanitsa mawotchi olowetsa/otulutsa parameter. Za example, ck_fr_out imadyetsa DDIO yathunthu munjira yotuluka.
ck_fr_out
ck_hr_mu
ck_hr_out
cke	Zolowetsa	Wotchi imathandizira.

Table 6. Zizindikiro za Interface Interface

Mawonekedwe omaliza amalumikiza GPIO IP pachimake ndi ma buffer a I/O.

Dzina la Signal	Mayendedwe	Kufotokozera
seriesterminationcontrol	Zolowetsa	Lowetsani kuchokera ku termination control block (OCT) kupita ku mabafa. Imayika buffer series impedance value.
parallelterminationcontrol	Zolowetsa	Lowetsani kuchokera ku termination control block (OCT) kupita ku mabafa. Imayika buffer parallel impedance value.

Table 7. Bwezeraninso Zizindikiro za Chiyankhulo

Mawonekedwe obwezeretsanso amalumikiza GPIO IP pachimake ndi ma DDIO.

Dzina la Signal	Mayendedwe	Kufotokozera
sclr	Zolowetsa	Kulowetsa momveka bwino. Palibe ngati mutsegula sset.
aclr	Zolowetsa	Asynchronous zomveka bwino. Kuthamanga kwambiri. Sizikupezeka ngati mutsegula aset.
katundu	Zolowetsa	Kuyika kwa Asynchronous. Kuthamanga kwambiri. Palibe ngati mutsegula aclr.
sset	Zolowetsa	Kuyika kwa synchronous. Palibe ngati mutsegula sclr.

Zambiri Zogwirizana
Mabasi Olowetsa ndi Kutuluka Mabasi Okwera ndi Otsika patsamba 12

Zizindikiro Zogawana

• Zolowetsa, zotuluka, ndi njira za OE zimagawana zizindikiro zomveka bwino komanso zokonzedweratu.
• Zotulutsa ndi njira ya OE imagawana mawotchi omwewo.

Data Bit-Order ya Data Interface

Chithunzi 9. Msonkhano wa Data Bit-Order

Chiwerengerochi chikuwonetsa dongosolo la ma data a din, dout ndi oe data.

• Ngati mtengo wa basi ya data ndi SIZE, LSB ili pamalo abwino kwambiri.
• Ngati mtengo wa basi ya data ndi 2 × SIZE, basi imapangidwa ndi mawu awiri a SIZE .
• Ngati kukula kwa basi ya data ndi 4 × SIZE, basi imapangidwa ndi mawu anayi a SIZE.
• LSB ili pamalo abwino kwambiri pa liwu lililonse.
• Liwu lakumanja kwambiri limatchula liwu loyamba lotuluka mabasi otuluka ndi liwu loyamba lobwera mabasi olowera.

Zambiri Zogwirizana
Njira yolowera patsamba 5

Kulowetsa ndi Kutulutsa Mabasi Okwera ndi Otsika

Ma bits apamwamba ndi otsika pazolowera kapena zotuluka amaphatikizidwa muzolowera za din ndi dout ndi mabasi otulutsa.

Lowetsani basi

Kwa din bus, ngati datain_h ndi datain_l ndizokwera komanso zotsika, m'lifupi mwake ndi datain_width:

• datain_h = din[(2 × datain_width – 1):datain_width]
• datain_l = din[(datain_width - 1):0]

Za example, kwa din[7:0] = 8'b11001010:

• datain_h = 4'b1100
• datain_l = 4'b1010

Mabasi Otuluka

Kwa basi ya dout, ngati dataout_h ndi dataout_l ndizokwera komanso zotsika, m'lifupi mwake ndi dataout_width:

• dataout_h = dout[(2 × dataout_width – 1):dataout_width]
• dataout_l = dout[(dataout_width - 1):0]

Za example, chifukwa [7:0] = 8'b11001010:

• detaout_h = 4'b1100
• detaout_l = 4'b1010

Zizindikiro za Chiyankhulo cha Data ndi Mawotchi Ogwirizana

Table 8. Zizindikiro za Chiyankhulo cha Data ndi Mawotchi Ogwirizana

Dzina la Signal	Kukonzekera kwa Parameter			Koloko
	Register Mode	Hafu Rate	Mawotchi Osiyana
din	Register yosavuta ZOCHITIKA	Kuzimitsa	Kuzimitsa	ck
	ZOCHITIKA	On	Kuzimitsa	ck_hr
	Register yosavuta ZOCHITIKA	Kuzimitsa	On	ck_mu
	ZOCHITIKA	On	On	ck_hr_mu
dout oe	Register yosavuta ZOCHITIKA	Kuzimitsa	Kuzimitsa	ck
	ZOCHITIKA	On	Kuzimitsa	ck_hr
	Register yosavuta ZOCHITIKA	Kuzimitsa	On	ck_ku
	ZOCHITIKA	On	On	ck_hr_out
sclr sset Zizindikiro zonse za pad	Register yosavuta ZOCHITIKA	Kuzimitsa	Kuzimitsa	ck
	ZOCHITIKA	On	Kuzimitsa	ck_fr
	Register yosavuta ZOCHITIKA	Kuzimitsa	On	Njira yolowera: ck_in Njira yotulutsira: ck_out
	ZOCHITIKA	On	On	Njira yolowera: ck_fr_in Njira yotulutsira: ck_fr_out

Kutsimikizira Kagwiritsidwe Ntchito Kazinthu ndi Kapangidwe Kapangidwe

Mutha kulozera ku Intel Quartus Prime compilation malipoti kuti mudziwe zambiri zamagwiritsidwe ntchito ndi momwe mumapangira.

1. Pa menyu, dinani Kukonza ➤ Yambani Kuphatikiza kuyendetsa kusonkhanitsa kwathunthu.
2. Pambuyo pokonza mapangidwewo, dinani Kukonza ➤ Lipoti Lophatikiza.
3. Kugwiritsa ntchito M'ndandanda wazopezekamo, yendani ku Fitter ➤ Gawo la Zothandizira.
   a. Kuti view chidziwitso chogwiritsa ntchito gwero, sankhani Chidule cha Kagwiritsidwe Ntchito ka Zothandizira.
   b. Kuti view chidziwitso chogwiritsa ntchito gwero, sankhani Kugwiritsa Ntchito Zothandizira ndi Entity.

GPIO Intel FPGA IP Parameter Zokonda

Mutha kukhazikitsa zoikamo za GPIO IP pachimake mu pulogalamu ya Intel Quartus Prime. Pali magulu atatu a zosankha: General, Bafa,ndi Olembetsa.

Table 9. GPIO IP Core Parameters - General

Parameter	Mkhalidwe	Makhalidwe Ololedwa	Kufotokozera
Mayendedwe a Data	-	Zolowetsa Zotulutsa  Bidir	Imatchula mayendedwe a data a GPIO.
Deta wide	-	1 mpaka 128	Imatchula m'lifupi mwa data.
Gwiritsani ntchito mayina adoko apamwamba	-	On Kuzimitsa	Gwiritsani ntchito mayina adoko omwewo monga Stratix V, Arria V, ndi Cyclone V zida. Za example, dout imakhala dataout_h ndi dataout_l, ndipo din imakhala datain_h ndi datain_l. Chidziwitso: Makhalidwe a madokowa ndi osiyana ndi zida za Stratix V, Arria V, ndi Cyclone V. Kuti mudziwe zambiri zokhudza kusamuka, onaninso zokhudzana ndi izi.

Table 10. GPIO IP Core Parameters - Buffer

Parameter	Mkhalidwe	Makhalidwe Ololedwa	Kufotokozera
Gwiritsani ntchito buffer yosiyana	-	On  Kuzimitsa	Mukayatsidwa, imathandizira ma buffers a I/O.
Gwiritsani ntchito pseudo differential buffer	Mayendedwe a Data = Zotuluka Gwiritsani ntchito buffer yosiyana = On	On  Kuzimitsa	Ngati yayatsidwa mumayendedwe otulutsa, imathandiza ma buffers a pseudo differential. Njirayi imayatsidwa yokha kuti iwonekere ngati muyatsa Gwiritsani ntchito buffer yosiyana.
Gwiritsani ntchito mabasi oyendetsa mabasi	Deta Direction = Input kapena Bidir Gwiritsani ntchito buffer yosiyana = Off	On  Kuzimitsa	Akayatsidwa, mabasi oyendetsa mabasi amatha kuyika chizindikiro pa pini ya I/O pamalo ake othamangitsidwa pomwe malo otuluka amakhala 1 kapena 0 koma osati kulepheretsa kwambiri.
Gwiritsani ntchito open drain output	Deta Direction = Zotulutsa kapena Bidir Gwiritsani ntchito buffer yosiyana = Off	On  Kuzimitsa	Mukayatsidwa, kutulutsa kotseguka kumathandizira kuti chipangizochi chizipereka ma siginecha owongolera mulingo wadongosolo monga kusokoneza ndi kulemba, zimathandizira ma siginoloji omwe angatsitsidwe ndi zida zingapo m'dongosolo lanu.
Yambitsani kutulutsa koyambitsa port	Mayendedwe a Data = Zotuluka	On  Kuzimitsa	Mukayatsidwa, imathandizira kulowetsa kwa ogwiritsa ntchito padoko la OE. Njirayi imayatsidwa yokha kuti igwirizane ndi njira ziwiri.
Yambitsani ma doko a seriestermination / paralleltermination	-	On  Kuzimitsa	Mukayatsidwa, imayatsa ma doko a seriesterminationcontrol ndi parallelterminationcontrol a buffer yotulutsa.

Table 11. GPIO IP Core Parameters - Registers

Parameter	Mkhalidwe	Makhalidwe Ololedwa	Kufotokozera
Register mode	-	Palibe  Kaundula yosavuta  ZOCHITIKA	Imatchula njira yolembetsa ya GPIO IP core: Palibe-Imatanthawuza kulumikizana kwa waya kosavuta kuchokera / kupita ku buffer. Kaundula yosavuta-Imanena kuti DDIO imagwiritsidwa ntchito ngati kaundula wamba mu single data-rate mode (SDR). The Fitter ikhoza kulongedza kaundulayu mu I/O. ZOCHITIKA- imafotokoza kuti IP core imagwiritsa ntchito DDIO.
Yambitsani doko lowoneka bwino / lokhazikika	Register mode = DDIO	Palibe  Zomveka  Kukonzekeratu	Imatchula momwe mungakhazikitsire doko lokhazikitsiranso synchronous. Palibe-Imayimitsa doko lokhazikitsiranso synchronous. Zomveka-Imayatsira doko la SCLR kuti lichotse zofananira. Kukonzekeratu-Imayatsa doko la SSET kuti likhazikitsidwe molumikizana.
Yambitsani doko lowoneka bwino / lokhazikika	Register mode = DDIO	Palibe  Zomveka  Kukonzekeratu	Imatchulanso momwe mungakhazikitsire doko la asynchronous reset. Palibe-Imayimitsa doko lokhazikika la asynchronous. Zomveka- Imayatsira doko la ACLR kuti lichotse zosinthika. Kukonzekeratu-Imathandizira doko la ASET kuti likhazikitsidwe mwadongosolo. Zizindikiro za ACLR ndi ASET ndizokwera kwambiri.
Yambitsani ma doko a wotchi	Register mode = DDIO	On  Kuzimitsa	On-Imawulula doko lothandizira (CKE) kuti likulole kuwongolera data ikatsekedwa kapena kutuluka. Chizindikirochi chimalepheretsa deta kuti idutse popanda kuwongolera. Kuzimitsa- khomo lothandizira mawotchi silimawululidwa ndipo deta nthawi zonse imadutsa mu registry yokha.
Hafu Rate logic	Register mode = DDIO	On  Kuzimitsa	Mukayatsidwa, imathandizira DDIO ya theka la mlingo.
Olekanitsa mawotchi / zotulutsa	Deta Direction = Bidir  Njira yolembetsa = Regista yosavuta kapena DDIO	On  Kuzimitsa	Akayatsidwa, imayatsa mawotchi osiyana (CK_IN ndi CK_OUT) kuti alowe ndi zotuluka munjira ziwiri.

Zambiri Zogwirizana

• Mabasi Olowetsa ndi Kutuluka Mabasi Okwera ndi Otsika patsamba 12
• Upangiri: Sinthanitsani datain_h ndi datain_l Madoko mu IP Yosamutsidwa patsamba 23

Register Packing

GPIO IP pachimake imakulolani kulongedza zolembera m'mphepete kuti musunge malo ndi kugwiritsa ntchito zida.

Mutha kukonza DDIO yathunthu panjira yolowera ndi kutulutsa ngati flip flop. Kuti muchite izi, onjezani ntchito za .qsf zomwe zalembedwa mu tebulo ili.

Table 12. Lembani Kulongedza Ntchito za QSF

Njira	Chithunzi cha QSF
Lowetsani kaundula	Ntchito ya QSF set_instance_assignment -name FAST_INPUT_REGISTER ON -to
Linanena bungwe kaundula kulongedza katundu	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to
Linanena bungwe yambitsani kaundula kulongedza	set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -ku

Zindikirani: Ntchito izi sizikutsimikizira kulongedza katundu. Komabe, ntchitozi zimathandiza a Fitter kupeza malo ovomerezeka. Apo ayi, Fitter imasunga flip flop pachimake.

GPIO Intel FPGA IP Nthawi

Kuchita kwa GPIO IP pachimake kumadalira zovuta za I / O ndi magawo a wotchi. Kuti mutsimikizire nthawi yosinthira GPIO yanu, Intel ikulimbikitsa kuti mugwiritse ntchito Timing Analyzer.

Zambiri Zogwirizana
Intel Quartus Prime Timing Analyzer

Zida Zanthawi

Zida za nthawi ya GPIO IP zimakhala ndi njira zitatu.

• Njira zolumikizira I/O—kuchokera ku FPGA kupita ku zida zolandirira zakunja komanso kuchokera ku zida zotumizira kunja kupita ku FPGA.
• Njira zolumikizirana ndi data ndi wotchi - kuchokera ku I/O kupita pachimake komanso kuyambira pachimake kupita ku I/O.
• Njira zosinthira—kuchokera pa theka kupita ku DDIO yathunthu, komanso kuchokera pamlingo wathunthu mpaka theka la DDIO.

Chidziwitso: The Timing Analyzer imagwira njira mkati mwa midadada ya DDIO_IN ndi DDIO_OUT ngati mabokosi akuda.

Chithunzi 10. Njira Zolowetsa Nthawi Zigawo

Chithunzi 11. Zigawo za Nthawi Yotulutsa Njira

Chithunzi 12. Chotulukapo Yambitsani Njira Zopangira Nthawi

Zinthu Zochedwa

Pulogalamu ya Intel Quartus Prime simangoyika zinthu zochedwa kuti ziwonjezeke pakuwunika nthawi ya I/O. Kuti mutseke nthawi kapena kukulitsa kuchedwa, ikani zinthu zochedwetsa pamanja pazokonda za Intel Quartus Prime file (.qsf).

Table 13. Kuchedwa Elements .qsf Ntchito

Tchulani ntchito izi mu .qsf kuti mupeze zochedwetsa.

Delay Element	.qsf Ntchito
Lowetsani Kuchedwa Element	set_instance_assignment to -dzina INPUT_DELAY_CHAIN ​​<0..63>
Chinthu Chochedwa Kutulutsa	set_instance_assignment to -dzina OUTPUT_DELAY_CHAIN ​​<0..15>
Kutulutsa Yambitsani Chigawo Chakuchedwa	set_instance_assignment to -dzina OE_DELAY_CHAIN ​​<0..15>

Kusanthula Nthawi

Pulogalamu ya Intel Quartus Prime sipanga zokha zoletsa za SDC za GPIO IP pachimake. Muyenera kulowa pamanja zoletsa nthawi.

Tsatirani malangizo a nthawi komanso mwachitsanzoamples kuwonetsetsa kuti Timing Analyzer imasanthula nthawi ya I/O molondola.

• Kuti mufufuze nthawi yoyenera ya njira za mawonekedwe a I/O, tchulani zopinga za mapini a data motsutsana ndi pini ya wotchi mu .sdc file.
• Kuti mufufuze nthawi yoyenera pamakina apakati, tanthauzirani makonda awa mu .sdc file:
  - Yang'anani ku zolembera zoyambira
  - Yang'anani pamakaundula a I/O kuti mulembetse mosavuta ndi mitundu ya DDIO

Zambiri Zogwirizana
AN 433: Kuletsa ndi Kusanthula Mawonekedwe Ogwirizana ndi Magwero
Limafotokoza njira zochepetsera ndikusanthula ma source-synchronous interfaces.

Single Data Rate Input Register

Chithunzi 13. Kaundula wa Data Rate Imodzi

Table 14. Single Data Rate Input Register .sdc Lamulo Examples

Lamulo	Lamula Example	Kufotokozera
create_clock	create_clock -name sdr_in_clk -period "100 MHz" sdr_in_clk	Amapanga zochunira za wotchi yolowera.
set_input_kuchedwa	set_input_delay -clock sdr_in_clk 0.15 sdr_in_data	Imalangiza Timing Analyzer kuti iwunike nthawi yolowetsa I/O ndikuchedwa kwa 0.15 ns.

Regista ya Zolowetsa za DDIO Zokwanira Zonse kapena Hafu

Mbali yolowera ya zolembera zolembera za DDIO zodzaza ndi theka ndi zofanana. Mutha kukakamiza dongosololi pogwiritsa ntchito wotchi yeniyeni kuti mufananize ndi transmitter yochokera ku FPGA.

Chithunzi 14. Kaundula wa Input wa DDIO Wokwanira kapena Half-Rate

Table 15. Full-Rate kapena Half-Rate DDIO Input Register .sdc Command Examples

Lamulo	Lamula Example	Kufotokozera
create_clock	create_clock -name virtual_clock - nthawi "200 MHz" create_clock -name ddio_in_clk -nthawi "200 MHz" ddio_in_clk	Pangani mawotchi a wotchi yeniyeni ndi wotchi ya DDIO.
set_input_kuchedwa	set_input_delay -clock virtual_clock 0.25 ddio_mu_data set_input_delay -add_delay -clock_kugwa -clock virtual_clock 0.25 ddio_mu_data	Lamulani Timing Analyzer kuti aunike m'mphepete mwa wotchi yabwino komanso m'mphepete mwawotchi yoyipa yakusamutsa. Dziwani -add_delay mu lamulo lachiwiri la set_input_delay.
khazikitsa_njira_zabodza	set_false_path -gwa_kuchokera virtual_clock -rise_to ddio_in_clk set_false_path -nyamuka_kuchokera pafupifupi_clock -fall_to ddio_in_clk	Langizani Timing Analyzer kuti isanyalanyaze m'mphepete mwa wotchi yabwino kupita ku register yoyipa yomwe idayambika, ndi m'mphepete mwa wotchi yoyipa kupita ku registry yabwino. Chidziwitso: Mafupipafupi a ck_hr akuyenera kukhala theka la ck_fr pafupipafupi. Ngati I/O PLL ikuyendetsa mawotchi, mungaganizire kugwiritsa ntchito lamulo la derive_pll_clocks .sdc.

Single Data Rate Output Register

Chithunzi 15. Kaundula wa Data Rate Limodzi

Table 16. Single Data Rate Output Register .sdc Command Examples

Lamulo	Lamula Example	Kufotokozera
create_clock ndi create_generated_clock	create_clock -name sdr_out_clk -nthawi "100 MHz" sdr_out_clk create_generated_clock -source sdr_out_clk -name sdr_out_outclk sdr_out_outclk	Pangani wotchi yoyambira ndi wotchi yotulutsa kuti mutumize.
set_output_kuchedwa	set_output_delay -clock sdr_out_clk 0.45 sdr_out_data	Imalangiza Timing Analyzer kuti ifufuze zomwe zatuluka kuti zitumize motsutsana ndi wotchi yotulutsa kuti itumize.

Kaundula wa Zotulutsa za DDIO Mokwanira kapena Hafu

Mbali yotulutsa ya zolembera za DDIO zamtundu wathunthu ndi theka ndizofanana.

Table 17. DDIO Output Register .sdc Lamulo Eksamples

Lamulo	Lamula Example	Kufotokozera
create_clock ndi create_generated_clock	create_clock -name ddio_out_fr_clk -nthawi "200 MHz" ddio_out_fr_clk create_generated_clock -source ddio_out_fr_clk -name ddio_out_fr_outclk ddio_out_fr_outclk	Pangani mawotchi ku DDIO ndi wotchi kuti mutumize.
set_output_kuchedwa	set_output_delay -clock ddio_out_fr_outclk 0.55 ddio_out_fr_data set_output_dey -add_delay -koloko_kugwa -koloko ddio_out_fr_outclk 0.55 ddio_out_fr_data	Langizani Timing Analyzer kuti ifufuze zabwino ndi zoyipa zomwe zili ndi wotchi yotulutsa.
khazikitsa_njira_zabodza	set_false_path -nyamuka_kuchokera ddio_out_fr_clk -fall_to ddio_out_fr_outclk set_false_path -gwa_kuchokera ddio_out_fr_clk -rise_to ddio_out_fr_outclk	Langizani Timing Analyzer kuti isanyalanyaze kukwera kwa wotchi yoyambira poyang'ana m'mphepete mwa wotchi yomwe ikutuluka, komanso m'mphepete mwa wotchi yomwe ikugwa poyang'ana m'mphepete mwawotchi yotuluka.

Malangizo Otseka Nthawi

Pa zolembera zolowetsa za GPIO, kutumiza kwa I/O kungathe kulephera nthawi yogwira ngati simukuyika unyolo wochedwa. Kulepheraku kumachitika chifukwa chakuchedwa kwa wotchiyo kuposa kuchedwa kwa data.

Kuti mukwaniritse nthawi yoyimitsa, onjezani kuchedwa panjira yolowera pogwiritsa ntchito njira yochedwa. Nthawi zambiri, unyolo wochedwa wolowera umakhala pafupifupi 60 ps pa sitepe pa 1 liwiro giredi. Kuti muchepetse kuchedwa kwacheni kuti mudutse nthawi, gawani kukhazikika kolakwika ndi 60 ps.

Komabe, ngati I/O PLL imayendetsa mawotchi a zolembera zolowetsa za GPIO (kaundula wosavuta kapena mawonekedwe a DDIO), mutha kukhazikitsa njira yolipirira kuti mupeze njira yolumikizirana. The Fitter idzayesa kukonza I/O PLL kuti ikhazikike bwino ndikugwirani mochedwa pakuwunikira nthawi ya I/O.

Pazotulutsa ndi zotulutsa za GPIO zimathandizira zolembetsa, mutha kuwonjezera kuchedwa kwa zomwe zatulutsidwa ndi wotchi pogwiritsa ntchito zotulutsa ndi zotulutsa zimathandizira unyolo wochedwa.

• Ngati muwona kuphwanya nthawi yokhazikitsa, mutha kuwonjezera machulukidwe a wotchi yochedwa.
• Ngati muwona kuphwanya nthawi, mutha kuwonjezera macheni acheni yotulutsa.

GPIO Intel FPGA IP Design Examples

GPIO IP core imatha kupanga kapangidwe kakaleamples zomwe zikugwirizana ndi kasinthidwe kanu ka IP mu mkonzi wa parameter. Mutha kugwiritsa ntchito zojambula izi kaleampkuchepera ngati maumboni olimbikitsa IP core komanso zomwe zikuyembekezeka pakuyerekeza.

Mutha kupanga ex designampkuchokera ku GPIO IP core parameter editor. Mukakhazikitsa magawo omwe mukufuna, dinani Pangani Exampndi Design. IP core imapanga kapangidwe kakaleampndi source files mu chikwatu chomwe mwafotokoza.

Chithunzi 16. Gwero Files mu Generated Design Exampndi Directory

Chidziwitso: The .qsys files ndi zogwiritsidwa ntchito mkati panthawi ya mapangidweample generation basi. Simungathe kusintha izi .qsys files.

GPIO IP Core Synthesizable Intel Quartus Prime Design Example

The synthesizeble design example ndi makina okonzekera Platform Designer omwe mungaphatikizepo mu projekiti ya Intel Quartus Prime.

Kupanga ndi Kugwiritsa Ntchito Design Example

Kuti apange kapangidwe ka Intel Quartus Prime example kuchokera ku gwero files, yendetsani lamulo lotsatirali pamapangidwe a example directory:

quartus_sh -t make_qii_design.tcl

Kuti mutchule chipangizo chenicheni chomwe mungagwiritse ntchito, yesani lamulo ili:

quartus_sh -t make_qii_design.tcl [device_name]

Zolemba za TCL zimapanga chikwatu cha qii chomwe chili ndi ed_synth.qpf project file. Mutha kutsegula ndikuphatikiza pulojekitiyi mu pulogalamu ya Intel Quartus Prime.

GPIO IP Core Simulation Design Example

Kapangidwe ka kayeseleledwe kakaleample imagwiritsa ntchito makonda anu apakati a GPIO IP kuti apange chitsanzo cha IP cholumikizidwa ndi dalaivala woyeserera. Dalaivala amapanga magalimoto mwachisawawa ndipo mkati mwake amayang'ana kuvomerezeka kwa data yotuluka.

Kugwiritsa ntchito design example, mutha kuyendetsa kayeseleledwe pogwiritsa ntchito lamulo limodzi, kutengera simulator yomwe mumagwiritsa ntchito. Kuyerekeza kukuwonetsa momwe mungagwiritsire ntchito GPIO IP pachimake.

Kupanga ndi Kugwiritsa Ntchito Design Example

Kupanga kapangidwe ka kayeseleledwe kakaleample kuchokera ku gwero files kwa Verilog simulator, yendetsani lamulo lotsatirali mu kapangidwe kakaleample directory:

quartus_sh -t make_sim_design.tcl

Kupanga kapangidwe ka kayeseleledwe kakaleample kuchokera ku gwero files ya VHDL yoyeseza, yendetsani lamulo lotsatirali mu kapangidwe kakaleample directory:

quartus_sh -t make_sim_design.tcl VHDL

Zolemba za TCL zimapanga chikwatu cha sim chomwe chili ndi ma subdirectories-chimodzi pa chida chilichonse chothandizira. Mutha kupeza zolemba za chida chilichonse chofananira m'makalata ofananira.

IP Migration Flow kwa Arria V, Cyclone V, ndi Stratix V Devices

Kuyenda kwa IP kusamuka kumakupatsani mwayi kusamuka ma ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, ndi ALTIOBUF IP cores a Arria V, Cyclone V, ndi Stratix V zida kupita ku GPIO IP pachimake cha Intel Arria 10 ndi Intel Cyclone 10 GX zida.

Kuthamanga kwa IP kumeneku kumakonza GPIO IP core kuti igwirizane ndi zoikamo za ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, ndi ALTIOBUF IP cores, kukulolani kuti mupangenso IP core.

Zindikirani: Ma IP cores ena amathandizira kusuntha kwa IP m'njira zapadera zokha. Ngati IP core yanu ili mumayendedwe omwe sakuthandizidwa, mungafunike kuyendetsa IP Parameter Editor ya GPIO IP core ndikukonzekera IP core pamanja.

Kusamutsa ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, ndi ALTIOBUF IP Cores

Kuti musamutsire ma cores anu a IP a ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, ndi ALTIOBUF kupita ku IP IP core ya GPIO Intel FPGA, tsatirani izi:

1. Tsegulani maziko anu a ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, kapena ALTIOBUF IP mu IP Parameter Editor.
2. Mu Banja la chipangizo chosankhidwa pano, sankhani Intel Arria 10 or Intel Cyclone 10 GX.
3. Dinani Malizitsani kuti mutsegule GPIO IP Parameter Editor.
   IP Parameter Editor imakonza zoikamo za GPIO IP zofananira ndi ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, kapena ALTIOBUF zoikamo.
4. Ngati pali zokonda zosagwirizana pakati pa ziwirizi, sankhani makonda atsopano othandizira.
5. Dinani Malizitsani kupanganso IP core.
6. M'malo mwa ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, kapena ALTIOBUF IP core instantition mu RTL ndi GPIO IP core.

Zindikirani: Mayina apakati a GPIO IP mwina sangafanane ndi ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, kapena ALTIOBUF IP mayina adoko. Chifukwa chake, kungosintha dzina loyambira la IP munthawi yomweyo sikungakhale kokwanira.

Zambiri Zogwirizana
Mabasi Olowetsa ndi Kutuluka Mabasi Okwera ndi Otsika patsamba 12

Malangizo: Sinthanitsani datain_h ndi datain_l Madoko mu IP Yosamutsidwa

Mukasamutsa GPIO IP yanu kuchokera ku zida zam'mbuyomu kupita ku GPIO IP core, mutha kuyatsa Gwiritsani ntchito mayina adoko apamwamba njira mu GPIO IP core parameter editor. Komabe, machitidwe a madoko awa mu GPIO IP pachimake ndi osiyana ndi ma IP cores omwe amagwiritsidwa ntchito pazida za Stratix V, Arria V, ndi Cyclone V.

GPIO IP pachimake imayendetsa madoko awa ku zolembera zotuluka pamphepete mwa wotchi iyi:

• datain_h-pamtunda wokwera wa outclock
• datain_l-pamphepete mwa kugwa kwa outclock

Ngati mudasamutsa IPO yanu ya GPIO kuchokera ku zida za Stratix V, Arria V, ndi Cyclone V, sinthanani madoko a datain_h ndi datain_l mukakhazikitsa IP yopangidwa ndi GPIO IP core.

Zambiri Zogwirizana
Mabasi Olowetsa ndi Kutuluka Mabasi Okwera ndi Otsika patsamba 12

GPIO Intel FPGA IP User Guide Archives

Mitundu ya IP ndi yofanana ndi mitundu ya Intel Quartus Prime Design Suite mpaka v19.1. Kuchokera ku Intel Quartus Prime Design Suite software version 19.2 kapena mtsogolo, ma IP cores ali ndi dongosolo latsopano la IP.

Ngati mtundu wa IP core sunatchulidwe, chiwongolero cha ogwiritsa ntchito pamtundu wakale wa IP akugwira ntchito.

IP Core Version	Wogwiritsa Ntchito
20.0.0	GPIO Intel FPGA IP User Guide: Intel Arria 10 ndi Intel Cyclone 10 GX Devices
19.3.0	GPIO Intel FPGA IP User Guide: Intel Arria 10 ndi Intel Cyclone 10 GX Devices
19.3.0	GPIO Intel FPGA IP User Guide: Intel Arria 10 ndi Intel Cyclone 10 GX Devices
18.1	GPIO Intel FPGA IP User Guide: Intel Arria 10 ndi Intel Cyclone 10 GX Devices
18.0	GPIO Intel FPGA IP User Guide: Intel Arria 10 ndi Intel Cyclone 10 GX Devices
17.1	Intel FPGA GPIO IP Core User Guide
17.0	Altera GPIO IP Core User Guide
16.1	Altera GPIO IP Core User Guide
16.0	Altera GPIO IP Core User Guide
14.1	Altera GPIO Megafunction User Guide
13.1	Altera GPIO Megafunction User Guide

Mbiri Yokonzanso Zolemba za GPIO Intel FPGA IP User Guide: Intel Arria 10 ndi Intel Cyclone 10 GX Devices

Document Version	Intel Quartus Prime Version	Mtundu wa IP	Zosintha
2021.07.15	21.2	20.0.0	Sinthani chithunzi chomwe chikuwonetsa chosavuta view ya njira yolowera yokha ya GPIO yosinthira dout[0] ku dout[3] ndi dout[3] ku dout[0].
2021.03.29	21.1	20.0.0	Kusintha nambala ya GPIO IP kukhala 20.0.0.
2021.03.12	20.4	19.3.0	Kusintha malangizo a IP kusamuka kuti afotokoze kuti GPIO IP imayendetsa datain_h pamphepete yokwera ndi datain_l pamphepete yakugwa.
2019.10.01	19.3	19.3.0	Mauthenga anakonza zolakwika mu .qsf assignment codes pamutu wokhudza zinthu zochedwetsa.
2019.03.04	18.1	18.1	Pamitu yokhudzana ndi njira yolowera, ndipo zotuluka ndi zotuluka zimathandizira njira: Anakonza zolemba pamitu kuti afotokoze kuti GPIO Intel FPGA IP sichirikiza kusanja kwamphamvu kwa mapini obwereza. Maulalo owonjezera ku PHY Lite for Parallel Interfaces Intel FPGA IP Core User Guide: Intel Stratix 10, Intel Arria 10, ndi Intel Cyclone 10 GX Devices kuti mumve zambiri za mapulogalamu omwe amafunikira kusanja kwamphamvu kwa mapini obwereza.
2018.08.28	18.0	18.0	Adalembanso chikalatacho kuchokera ku Intel FPGA GPIO IP Core User Guide kupita ku GPIO Intel FPGA IP User Guide: Intel Arria 10 ndi Intel Cyclone 10 GX Devices. Adawonjezera ulalo ku kalozera wa ogwiritsa ntchito a Intel Stratix 10 GPIO IP.  Adasinthidwanso IP kuchokera ku "Intel FPGA GPIO" kukhala "GPIO Intel FPGA IP".  Konzani zochitika za "clk_fr" ndi "clk_hr" mpaka "ck_fr" ndi "ck_hr".  Sinthani njira yolowera ya GPIO IP ndi zithunzi zotuluka kuti muwonetse mayina enieni amtundu wa IP.

Tsiku	Baibulo	Zosintha
Novembala 2017	2017.11.06	Thandizo lowonjezera la zida za Intel Cyclone 10 GX. Sinthani mayina azizindikiro muzithunzi kuti agwirizane ndi mayina azizindikiro mu GPIO IP pachimake. Anawonjezera njira yotulutsa waveform. Adasinthidwanso "Altera GPIO IP core" kukhala "Intel FPGA GPIO IP core". Adasinthidwanso "Altera IOPLL IP core" kukhala "Intel FPGA IOPLL IP core". Anasinthidwanso "TimeQuest Timing Analyzer" kukhala "Timing Analyzer". Adasinthidwanso "Qsys" kukhala "Pulatform Designer". Kufotokozera kuti zizindikiro za ASET ndi ACLR ndizogwira ntchito.
Meyi 2017	2017.05.08	Sinthani tebulo lolemba magawo a GPIO buffer kuti mufotokoze momwe zinthu zilili Gwiritsani ntchito mabasi oyendetsa mabasi parameter njira. Adasinthidwa kukhala Intel.
Okutobala 2016	2016.10.31	Sinthani mawonekedwe anjira yolowera. Adawonjeza mutu wofotokoza zokwera ndi zotsika m'mabasi a din ndi dout.
Ogasiti 2016	2016.08.05	Zolemba zowonjezera zokhudzana ndi chithandizo champhamvu cha OCT mu GPIO IP pachimake. Kusintha mutu wokhudza zokonda za parameter kuti muwongolere kulondola komanso kumveka bwino. Zasinthidwa gawo la kupanga kapangidwe kakaleample. Adawonjeza mutu wotsogola wokhudza machitidwe a madoko otengera mbiri yanu mukasamukira ku GPIO IP core kuchokera pazida za Stratix V, Arria V, ndi Cyclone V. Lembaninso ndikusintha chikalatacho kuti chimveke bwino komanso kuti chizidziwika mosavuta. Zosintha za Quartus II kukhala Quartus Prime.
Ogasiti 2014	2014.08.18	Zowonjezera nthawi. Zolemba zowonjezera zolongedza. Zowonjezedwa Gwiritsani ntchito mayina adoko apamwamba parameter. Iyi ndi parameter yatsopano. Zolemba zowonjezera zolongedza. M'malo mwa mawu akuti megafunction ndi IP core.
Novembala 2013	2013.11.29	Kutulutsidwa koyamba.

Tumizani Ndemanga

GPIO Intel FPGA IP User Guide: Intel Arria 10 ndi Intel Cyclone 10 GX Devices

Zolemba / Zothandizira

Intel GPIO Intel FPGA IP [pdf] Buku Logwiritsa Ntchito GPIO Intel FPGA IP, GPIO, Intel FPGA IP, FPGA IP

Maumboni

• Buku Logwiritsa Ntchito