F-Tile Interlaken Intel FPGA IP Design Example

Quick Start Guide

F-Tile Interlaken Intel® FPGA IP pachimake imapereka testbench yoyeserera. Kapangidwe ka hardware example yomwe imathandizira kuphatikiza ndi kuyesa kwa hardware ipezeka mu Intel Quartus® Prime Pro Edition software version 21.4. Mukapanga zojambula zakaleampndi, mkonzi wa parameter amangopanga files zofunika kuyerekezera, kusonkhanitsa, ndi kuyesa mapangidwe.
Testbench ndi kapangidwe example imathandizira mawonekedwe a NRZ ndi PAM4 pazida za F-tile. F-Tile Interlaken Intel FPGA IP core imapanga zojambula zakaleampLes pazophatikizidwira zotsatirazi za kuchuluka kwa mayendedwe ndi mitengo ya data.

Kuphatikizika kwa IP kwa Nambala ya Misewu ndi Mitengo ya Data
Zophatikizira zotsatirazi zimathandizidwa mu pulogalamu ya Intel Quartus Prime Pro Edition 21.3. Zosakaniza zina zonse zidzathandizidwa mu mtundu wamtsogolo wa Intel Quartus Prime Pro Edition.

Nambala ya Misewu	Mtengo wa Lane (Gbps)
	6.25	10.3125	12.5	25.78125	53.125
4	Inde	-	Inde	Inde	-
6	-	-	-	Inde	Inde
8	-	-	Inde	Inde	-
10	-	-	Inde	Inde	-
12	-	Inde	Inde	Inde	-

Chithunzi 1.Masitepe a Kupititsa patsogolo kwa Design Example

Zindikirani: Kuphatikiza ndi Kuyesa kwa Hardware kudzapezeka mu pulogalamu ya Intel Quartus Prime Pro Edition 21.4.
F-Tile Interlaken Intel FPGA IP core design example imathandizira zotsatirazi:

• Internal TX to RX serial loopback mode
• Amapanga mapaketi okhazikika
• Mayeso owerengera paketi
• Kutha kugwiritsa ntchito System Console kukhazikitsanso mapangidwe kuti ayesenso

Chithunzi 2.Chojambula cha Block chapamwamba

Zambiri Zogwirizana

• F-Tile Interlaken Intel FPGA IP User Guide
• F-Tile Interlaken Intel FPGA IP Release Notes

Zofunikira pa Hardware ndi Mapulogalamu

Kuyesa example design, gwiritsani ntchito zida ndi mapulogalamu awa:

• Pulogalamu ya Intel Quartus Prime Pro Edition 21.3
• System Console
• Simulator Yothandizira:
  • Synopsy* VCS*
  • Zithunzi za VCS MX
  • Siemens* EDA ModelSim* SE kapena Questa*

Zindikirani:  Thandizo la Hardware la kapangidwe kakaleample ipezeka mu pulogalamu ya Intel Quartus Prime Pro Edition 21.4.

Kupanga Mapangidwe

Chithunzi 3. Ndondomeko

Tsatirani izi kuti mupange zojambula zakaleample ndi testbench:

1. Mu pulogalamu ya Intel Quartus Prime Pro Edition, dinani File ➤ New Project Wizard kuti mupange pulojekiti yatsopano ya Intel Quartus Prime, kapena dinani File ➤ Open Project kuti mutsegule pulojekiti yomwe ilipo ya Intel Quartus Prime. Wizard imakulimbikitsani kuti mutchule chipangizo.
2. Tchulani chipangizo cha banja la Agilex ndikusankha chipangizo chokhala ndi F-Tile pamapangidwe anu.
3. Mu IP Catalog, pezani ndikudina kawiri F-Tile Interlaken Intel FPGA IP. Zenera la New IP Variant likuwonekera.
4. Tchulani dzina lapamwamba pakusintha kwanu kwa IP. Mkonzi wa parameter amasunga zosintha za IP mu a file dzina .ip.
5. Dinani Chabwino. The parameter editor ikuwonekera.

Chithunzi 4. Exampndi Design Tab

6. Pa IP tabu, tchulani magawo anu a IP core kusiyana.
7. Pa Eksample Design tabu, sankhani Simulation njira kuti mupange testbench.
Chidziwitso: Njira ya kaphatikizidwe ndi ya hardware example design, yomwe ipezeka mu Intel Quartus Prime Pro Edition software version 21.4.
8. Pakuti Generated HDL Format, onse Verilog ndi VHDL njira zilipo.
9. Dinani Pangani Eksampndi Design. Sankhani Exampzenera la Design Directory likuwonekera.
10. Ngati mukufuna kusintha kapangidwe kakaleample chikwatu njira kapena dzina kuchokera zosasintha zomwe zikuwonetsedwa (ilk_f_0_example_design), sakatulani njira yatsopano ndikulemba mawonekedwe atsopanoample directory name.
11. Dinani OK.

Zindikirani: Mu F-Tile Interlaken Intel FPGA IP kapangidwe example, SystemPLL imakhazikika yokha, ndikulumikizidwa ku F-Tile Interlaken Intel FPGA IP core. The SystemPLL hierarchy njira mu kapangidwe example ndi:

example_design.test_env_inst.test_dut.dut.pll

The SystemPLL mu kapangidwe example amagawana wotchi yofananira ya 156.26 MHz ngati Transceiver.

Kapangidwe ka Kalozera

F-Tile Interlaken Intel FPGA IP core imapanga zotsatirazi files kwa kapangidwe exampLe:
Chithunzi 5. Kapangidwe ka Kalozera

Table 2. Mapangidwe a Hardware Example File Kufotokozera
Izi files muample_installation_dir>/ilk_f_0_example_design directory.

File Mayina	Kufotokozera
example_design.qpf	Intel Quartus Prime Project file.
example_design.qsf	Zokonda pa Intel Quartus Prime project file
example_design.sdc jtag_timing_template.sdc	Synopsys Design Constraint file. Mutha kukopera ndikusintha pamapangidwe anu.
sysconsole_testbench.tcl	Chachikulu file kuti mupeze System Console

Zindikirani: Thandizo la Hardware la kapangidwe kakaleample ipezeka mu pulogalamu ya Intel Quartus Prime Pro Edition 21.4.

Table 3. Testbench File Kufotokozera

Izi file ndi muample_installation_dir>/ilk_f_0_example_design/ example_design/rtl chikwatu.

File Dzina	Kufotokozera
pamwamba_tb.sv	Testbench yapamwamba kwambiri file.

Table 4. Testbench Scripts

Izi files muample_installation_dir>/ilk_f_0_example_design/ example_design/testbench directory

File Dzina	Kufotokozera
run_vcs.sh	Synopsys VCS script yoyendetsa testbench.
run_vcsmx.sh	Synopsys VCS MX script yoyendetsa testbench.
run_mentor.tcl	The Siemens EDA ModelSim SE kapena Questa script kuyendetsa testbench.

Kutsanzira Design Exampndi Testbench

Chithunzi 6. Ndondomeko

Tsatirani izi kuti muyesere testbench:

1. Pakulamula, sinthani ku bukhu la testbench simulation. Njira yachidule ndiample_installation_dir>/example_design/ testbench.
2. Yendetsani script yoyeserera ya simulator yothandizidwa yomwe mungasankhe. Zolembazo zimaphatikiza ndikuyendetsa testbench mu simulator. Zolemba zanu ziyenera kuyang'ana kuti SOP ndi EOP ziwerengero zofananira pambuyo pomaliza.

Table 5. Masitepe Kuthamanga Kayeseleledwe

Woyeserera	Malangizo
Zithunzi za VCS	Mu mzere wolamula, lembani:   sh run_vcs.sh
Chithunzi cha VCS MX	Mu mzere wolamula, lembani:   sh run_vcsmx.sh
ModelSim SE kapena Questa	Mu mzere wolamula, lembani:   vsim -do run_mentor.tcl Ngati mukufuna kuyerekezera popanda kubweretsa ModelSim GUI, lembani:   vsim -c -do run_mentor.tcl

3. Unikani zotsatira zake. Kuyerekeza kopambana kumatumiza ndikulandila mapaketi, ndikuwonetsa "Test PASSED".

Testbench ya kapangidwe kakaleampamamaliza ntchito zotsatirazi:

• Imakhazikitsa F-Tile Interlaken Intel FPGA IP pachimake.
• Imasindikiza mawonekedwe a PHY.
• Imafufuza malire a metaframe (SYNC_LOCK) ndi malire a mawu (block) (WORD_LOCK).
• Imadikirira kuti mayendedwe apawokha atsekedwe ndikuyanjanitsidwa.
• Amayamba kutumiza mapaketi.
• Imafufuza ziwerengero za paketi:
  • CRC24 zolakwika
  • SOPs
  • Zithunzi za EOPs

Zotsatirazi sample output ikuwonetsa kuyesa koyeserera kopambana:

Kupanga Design Example

1. Onetsetsani kuti example design generation yatha.
2. Mu pulogalamu ya Intel Quartus Prime Pro Edition, tsegulani pulojekiti ya Intel Quartus Primeample_installation_dir>/example_design.qpf>.
3. Pa Processing menyu, dinani Start Compilation.

Design Example Kufotokozera

Mapangidwe example akuwonetsa magwiridwe antchito a Interlaken IP core.

Design Exampndi Components

Example design imagwirizanitsa mawotchi amtundu wa PLL ndi mawotchi ofunikira. Example design imakonza IP core mumayendedwe a loopback yamkati ndikupanga mapaketi pa IP core TX yosinthira data ya ogwiritsa ntchito. IP core imatumiza mapaketi awa panjira yamkati ya loopback kudzera pa transceiver.
Pambuyo pa IP core receiver ilandila mapaketi panjira ya loopback, imayang'anira mapaketi a Interlaken ndikuwatumiza pa mawonekedwe osinthira a RX. Example design imayang'ana kuti mapaketiwo adalandiridwa ndikufalitsidwa.
Mapangidwe a F-Tile Interlaken Intel IP example ili ndi zigawo zotsatirazi:

1. F-Tile Interlaken Intel FPGA IP core
2. Packet Generator ndi Packet Checker
3. F-Tile Reference ndi System PLL Wotchi Intel FPGA IP core

Zizindikiro za Interface

Table 6. Design Exampndi Interface Signals

Dzina la Port	Mayendedwe	M'lifupi (Bits)	Kufotokozera
mgmt_clk	Zolowetsa	1	Kulowetsa wotchi yadongosolo. Wotchi pafupipafupi iyenera kukhala 100 MHz.
pll_ref_clk	Zolowetsa	1	Wotchi yowonetsera transceiver. Imayendetsa RX CDR PLL.
rx_pin	Zolowetsa	Nambala yamayendedwe	Pini ya data yolandila SERDES.
tx_pin	Zotulutsa	Nambala yamayendedwe	Tumizani pini ya data ya SERDES.
rx_pin_n(1)	Zolowetsa	Nambala yamayendedwe	Pini ya data yolandila SERDES.
tx_pin_n(1)	Zotulutsa	Nambala yamayendedwe	Tumizani pini ya data ya SERDES.
mac_clk_pll_ref	Zolowetsa	1	Chizindikirochi chiyenera kuyendetsedwa ndi PLL ndipo chiyenera kugwiritsa ntchito wotchi yomweyi yomwe imayendetsa pll_ref_clk. Chizindikirochi chimapezeka mumitundu yosiyanasiyana ya zida za PAM4 zokha.
usr_pb_reset_n	Zolowetsa	1	Konzanso dongosolo.

(1) Imapezeka mumitundu ya PAM4 yokha.

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa chakugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito.
*Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

Lembani Mapu

Zindikirani:

• Design Example registry adilesi imayamba ndi 0x20** pomwe Interlaken IP core registry adilesi imayamba ndi 0x10 **.
• Adilesi ya F-tile PHY imayamba ndi 0x30** pomwe adilesi ya F-tile FEC imayamba ndi 0x40**. Kulembetsa kwa FEC kumangopezeka mu PAM4 mode.
• Khodi yofikira: RO—Werengani Pokha, ndi RW—Werengani/Lembani.
• System console imawerenga zojambula zakaleample amalembetsa ndi kupereka lipoti mayeso pa zenera.

Table 7. Design Exampndi Register Mapu

Offset	Dzina	Kufikira	Kufotokozera
8h00 ku	Zosungidwa
8h01 ku	Zosungidwa
8h02 ku	Kusintha kwadongosolo kwa PLL	RO	Ma bits otsatirawa akuwonetsa pempho la dongosolo la PLL ndikuyambitsanso mtengo: • Pang'ono [0] - sys_pll_rst_req • Pang'ono [1] - sys_pll_rst_en
8h03 ku	Njira ya RX yolumikizidwa	RO	Imawonetsa njira ya RX.
8h04 ku	MAWU otsekedwa	RO	[NUM_LANES–1:0] – Chizindikiritso cha malire cha Mawu (chidacho).
8h05 ku	Kulunzanitsa kwatsekedwa	RO	[NUM_LANES–1:0] - Kulunzanitsa kwa Metaframe.
8'h06 - 8'h09	Chiwerengero cha zolakwika za CRC32	RO	Ikuwonetsa kuchuluka kwa zolakwika za CRC32.
8h0a ku	Chiwerengero cha zolakwika za CRC24	RO	Ikuwonetsa kuchuluka kwa zolakwika za CRC24.
8h0b ku	Kusefukira/Kuyenda kwapansi	RO	Zizindikiro zotsatirazi zikuwonetsa: • Pang'ono [3] - chizindikiro cha TX pansi • Pang'ono [2] - chizindikiro cha kusefukira kwa TX • Pang'ono [1] - chizindikiro cha RX kusefukira
8h0c ku	Mtengo wa SOP	RO	Imawonetsa nambala ya SOP.
8h0d ku	Mtengo wa EOP	RO	Imawonetsa nambala ya EOP
8h0e	Chiwerengero cha zolakwika	RO	Ikuwonetsa kuchuluka kwa zolakwika zotsatirazi: • Kutayika kwa njira • Mawu oletsa malamulo • Mapangidwe osaloledwa • Chizindikiro cha SOP kapena EOP chikusoweka
8h0f ku	send_data_mm_clk	RW	Lembani 1 mpaka pang'ono [0] kuti mutsegule chizindikiro cha jenereta.
8h10 ku	Cholakwika cha Checker		Imawonetsa cholakwika cha cheki. (Zolakwika za data za SOP, cholakwika cha nambala ya Channel, ndi vuto la data la PLD)
8h11 ku	System PLL loko	RO	Bit [0] imasonyeza chizindikiro cha PLL.
8h14 ku	Mtengo wa TX SOP	RO	Imawonetsa nambala ya SOP yopangidwa ndi jenereta ya paketi.
8h15 ku	Mtengo wa TXEOP	RO	Ikuwonetsa nambala ya EOP yopangidwa ndi jenereta ya paketi.
8h16 ku	Paketi yosalekeza	RW	Lembani 1 mpaka pang'ono [0] kuti mutsegule paketi yopitilira.
anapitiriza…

Offset	Dzina	Kufikira	Kufotokozera
8h39 ku	Chiwerengero cha zolakwika za ECC	RO	Imawonetsa kuchuluka kwa zolakwika za ECC.
8h40 ku	ECC yakonza zolakwika	RO	Ikuwonetsa kuchuluka kwa zolakwika za ECC zokonzedwa.
8h50 ku	tile_tx_rst_n	WO	Kubwezeretsanso matailosi ku SRC ya TX.
8h51 ku	tile_rx_rst_n	WO	Kubwezeretsanso matailosi ku SRC kwa RX.
8h52 ku	tile_tx_rst_ack_n	RO	Kukhazikitsanso matayala kuvomereza kuchokera ku SRC ya TX.
8h53 ku	tile_rx_rst_ack_n	RO	Kukhazikitsanso matayala kuvomereza kuchokera ku SRC kwa RX.

Bwezerani

Mu F-Tile Interlaken Intel FPGA IP pachimake, mumayambitsa kukonzanso (reset_n=0) ndikugwira mpaka IP core itabwezanso kuvomereza (reset_ack_n=0). Kukonzanso kukachotsedwa (reset_n=1), kubwezeretsanso kuvomereza kumabwereranso momwe idayambira.
(konzanso_ack_n=1). Mu kapangidwe exampLero, kaundula wa rst_ack_sticky amakhala ndi chitsimikiziro chobwezeretsanso ndikuyambitsa kuchotsedwanso (reset_n=1). Mungagwiritse ntchito njira zina zomwe zikugwirizana ndi zosowa zanu.

Zofunika: Muzochitika zilizonse zomwe serial loopback yamkati ikufunika, muyenera kumasula TX ndi RX ya F-tile padera mu dongosolo linalake. Onani script ya system console kuti mudziwe zambiri.

Chithunzi 7. Bwezeretsani Zotsatizana mu NRZ Mode

Chithunzi 8.Bwezeretsani Sequence mu PAM4 Mode

F-Tile Interlaken Intel FPGA IP Design Exampndi User Guide Archives

Ngati mtundu wa IP core sunatchulidwe, chiwongolero cha ogwiritsa ntchito pamtundu wakale wa IP akugwira ntchito.

Intel Quartus Prime Version	IP Core Version	Wogwiritsa Ntchito
21.2	2.0.0	F-Tile Interlaken Intel FPGA IP Design Exampndi User Guide

Mbiri Yokonzanso Zolemba za F-Tile Interlaken Intel FPGA IP Design Exampndi User Guide

Document Version	Intel Quartus Prime Version	Mtundu wa IP	Zosintha
2021.10.04	21.3	3.0.0	• Thandizo lowonjezera la njira zatsopano zophatikizira. Kuti mudziwe zambiri, onani Table: Kuphatikiza kwa IP kwa Nambala ya Misewu ndi Mtengo wa Data. • Sinthani mndandanda wa zoyeserera zomwe zimathandizira pagawo: Zofunikira pa Hardware ndi Mapulogalamu. • Onjezani zolembetsa zatsopano mugawo: Lembani Mapu.
2021.06.21	21.2	2.0.0	Kutulutsidwa koyamba.

Zolemba / Zothandizira

Intel F-Tile Interlaken Intel FPGA IP Design Example [pdf] Buku Logwiritsa Ntchito F-Tile Interlaken Intel FPGA IP Design Example, F-Tile, Interlaken Intel FPGA IP Design Exampndi, Intel FPGA IP Design Exampndi, IP Design Exampndi, Design Example

Maumboni

• Buku Logwiritsa Ntchito