25G Ethernet Intel® FPGA IP Release Notes
Wogwiritsa Ntchito
25G Ethernet Intel FPGA IP Release Notes (Zida za Intel Agilex)
Mitundu ya Intel® FPGA IP imafanana ndi mitundu ya Intel Quartus® Prime Design Suite mpaka v19.1. Kuyambira mu Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP ili ndi ndondomeko yatsopano yomasulira.
Nambala ya Intel FPGA IP (XYZ) imatha kusintha ndi mtundu uliwonse wa pulogalamu ya Intel Quartus Prime. Kusintha kwa:
- X ikuwonetsa kukonzanso kwakukulu kwa IP. Mukasintha pulogalamu ya Intel Quartus Prime, muyenera kukonzanso IP.
- Y akuwonetsa kuti IP ili ndi zatsopano. Panganinso IP yanu kuti muphatikizepo zatsopanozi.
- Z ikuwonetsa kuti IP imaphatikizapo zosintha zazing'ono. Panganinso IP yanu kuti ikhale ndi zosinthazi.
1.1. 25G Efaneti Intel FPGA IP v1.0.0
Gulu 1. v1.0.0 2022.09.26
| Intel Quartus Prime Version | Kufotokozera | Zotsatira |
| 22.3 | Thandizo lowonjezera la banja la chipangizo cha Intel Agilex™ F-tile. • Kuthamanga kwa 25G kokha kumathandizidwa. • 1588 Precision Time Protocol sichimathandizidwa. |
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Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa cha kugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito. *Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.
ISO
9001:2015
Olembetsedwa
25G Ethernet Intel FPGA IP Release Notes (Zida za Intel Stratix 10)
Ngati chikalata chomasulidwa sichikupezeka pamtundu wina wa IP, IP sisintha mu mtunduwo. Kuti mumve zambiri zakusintha kwa IP kutulutsa mpaka v18.1, onani Intel Quartus Prime Design Suite Update Release Notes.
Mitundu ya Intel FPGA IP imafanana ndi mitundu ya Intel Quartus Prime Design Suite mpaka v19.1. Kuyambira mu Intel Quartus Prime Design Suite software version 19.2, Intel
FPGA IP ili ndi njira yatsopano yosinthira.
Nambala ya Intel FPGA IP (XYZ) imatha kusintha ndi mtundu uliwonse wa pulogalamu ya Intel Quartus Prime. Kusintha kwa:
- X ikuwonetsa kukonzanso kwakukulu kwa IP. Mukasintha pulogalamu ya Intel Quartus Prime, muyenera kukonzanso IP.
- Y akuwonetsa kuti IP ili ndi zatsopano. Panganinso IP yanu kuti muphatikizepo zatsopanozi.
- Z ikuwonetsa kuti IP imaphatikizapo zosintha zazing'ono. Panganinso IP yanu kuti ikhale ndi zosinthazi.
Zambiri Zogwirizana
- Intel Quartus Prime Design Suite Update Release Notes
- 25G Ethernet Intel Stratix®10 FPGA IP User Guide Archives
- 25G Ethernet Intel Stratix® 10 FPGA IP Design Exampndi User Guide Archives
- Errata ya 25G Ethernet Intel FPGA IP mu Knowledge Base
2.1. 25G Efaneti Intel FPGA IP v19.4.1
Gulu 2. v19.4.1 2020.12.14
| Intel Quartus Prime Version | Kufotokozera | Zotsatira |
| 20.4 | Kusintha kwautali pamafelemu a VLAN: • M'matembenuzidwe am'mbuyomu a 25G Ethernet Intel FPGA IP, zolakwika zazikuluzikulu zimatsimikiziridwa pamene zotsatirazi zakwaniritsidwa: 1. VLAN a. Kuzindikira kwa VLAN ndikoyatsidwa. b. IP imatumiza/kulandira mafelemu okhala ndi utali wofikira kutalika kwa chimango cha TX/RX kuphatikiza 1 mpaka 4 octets. 2. SVLAN a. Kuzindikira kwa SVLAN ndikoyatsidwa. b. IP imatumiza/kulandira mafelemu okhala ndi utali wofikira kutalika kwa chimango cha TX/RX kuphatikiza 1 mpaka 8 octets. • Mu mtundu uwu, IP yasinthidwa kuti ikonze izi. |
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| Kusintha mawonekedwe a Avalon® omwe amakumbukiridwa pokumbukira mawonekedwe_* kuti mupewe kutha kwa mamapu a Avalon panthawi yowerengera ma adilesi omwe palibe: • M'matembenuzidwe am'mbuyomu a 25G Ethernet Intel FPGA IP, mawonekedwe a Avalon memory-mapped amawerengedwa ku ma adilesi omwe palibe pa status_* mawonekedwe angatsimikizire status_waitrequest mpaka pempho la Avalon memorymapped master litatha. Nkhaniyi tsopano yakonzedwa kuti isagwire ntchito yodikirira pomwe adilesi yomwe palibe ikupezeka. |
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| Zosintha za RS-FEC tsopano zimathandizira 100% kudutsa. | - |
2.2. 25G Efaneti Intel FPGA IP v19.4.0
Gulu 3. v19.4.0 2019.12.16
| Intel Quartus Prime Version | Kufotokozera | Zotsatira |
| 19.4 | rx_am_lock kusintha kwamakhalidwe: • M'matembenuzidwe am'mbuyomu a 25G Ethernet Intel FPGA IP, chizindikiro cha rx_am_lock chimachita chimodzimodzi ndi rx_block_lock pamitundu yonse. • Mu mtundu uwu, za RSFEC zoyatsa mitundu yosiyanasiyana ya IP, rx_am_lock tsopano ikunena loko yolumikizira ikakwaniritsidwa. Kwa zosintha zomwe sizili ndi RSFEC, rx_am_lock imagwirabe ntchito ngati rx_block_lock. |
Chizindikiro cha mawonekedwe, rx_am_lock, chimachita mosiyana ndi matembenuzidwe am'mbuyomu amitundu yothandizidwa ndi RSFEC. |
| Kusintha Paketi Yoyambira ya RX MAC: • M'matembenuzidwe am'mbuyomu, RX MAC imangoyang'ana zilembo za START kuti mudziwe chiyambi cha paketi. • Mu mtundu uwu, RX MAC tsopano imayang'ana mapaketi akubwera a Start of Frame Delimiter (SFD), kuwonjezera pa START character mwachisawawa. • Ngati njira yopititsira patsogolo yayatsidwa, MAC imayang'ana zilembo za START zokha kuti zilore kuyambika kwachizolowezi. |
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| Onjezani kaundula watsopano kuti mutsegule zoyambira: • M'marejista a RX MAC, kaundula pa offset 0x50A [4] akhoza kulembedwa kwa 1 kuti athe kuyang'ana koyambirira. Register iyi ndi "osasamala" pomwe mawu oyambira atsegulidwa. |
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2.3. 25G Efaneti Intel FPGA IP v19.3.0
Gulu 4. v19.3.0 2019.09.30
| Intel Quartus Prime Version | Kufotokozera | Zotsatira |
| 19.3 | Kwa mtundu wa MAC+PCS+PMA, dzina la gawo la transceiver wrapper tsopano lapangidwa mwamphamvu. Izi zimalepheretsa kugundana kosafunika kwa ma module ngati ma IP angapo akugwiritsidwa ntchito pamakina. | - |
2.4. 25G Efaneti Intel FPGA IP v19.2.0
Gulu 5. v19.2.0 2019.07.01
| Intel Quartus Prime Version | Kufotokozera | Zotsatira |
| 19.2 | Design Example kwa 25G Ethernet Intel FPGA IP: • Sinthani njira yopangira zida za Intel Stratix® 10 kuchokera ku Intel Stratix 10 L-Tile GX Transceiver Signal Integrity Development Kit kupita ku Intel Stratix 10 10 GX Signal Integrity L-Tile (Production) Zida Zachitukuko. |
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2.5. 25G Efaneti Intel FPGA IP v19.1
Gulu 6. v19.1 Epulo 2019
| Kufotokozera | Zotsatira |
| Onjezani chinthu chatsopano - Adaptive mode ya RX PMA Adaptation: • Yawonjeza gawo latsopano—Yambitsani zoyambitsa zosintha zokha za RX PMA CTLE/DFE mode. |
Zosinthazi ndizosankha. Ngati simukweza IP yanu pachimake, ilibe chatsopanochi. |
| Anapatsanso dzina la Enable Altera Debug Master Endpoint (ADME) kuti Muthandize Native PHY Debug Master Endpoint (NPDME) monga momwe Intel idasinthira mu pulogalamu ya Intel Quartus Prime Pro Edition. Pulogalamu ya Intel Quartus Prime Standard Edition ikugwiritsabe ntchito Enable Altera Debug Master Endpoint (ADME). | - |
2.6. 25G Efaneti Intel FPGA IP v18.1
Gulu 7. Mtundu wa 18.1 September 2018
| Kufotokozera | Zotsatira |
| Adawonjeza chinthu chatsopano-Elective PMA: • Anawonjezera parameter yatsopano—Core Variants. |
Zosinthazi ndizosankha. Ngati simukweza IP core yanu, ilibe zatsopanozi. |
| • Anawonjezera chizindikiro chatsopano cha 1588 Precision Time Protocol Interface—latency_sclk. | |
| Design Example kwa 25G Ethernet Intel FPGA IP: Adasinthidwanso njira yopangira zida za Intel Stratix 10 kuchokera ku Stratix 10 GX FPGA Development Kit kupita ku Stratix 10 L-Tile GX Transceiver Signal Integrity Development Kit. |
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Zambiri Zogwirizana
- 25G Ethernet Intel Stratix 10 FPGA IP User Guide
- 25G Ethernet Intel Stratix 10 FPGA IP Design Exampndi User Guide
- Errata ya 25G Ethernet IP core mu Knowledge Base
2.7. 25G Efaneti Intel FPGA IP v18.0
Gulu 8. Mtundu wa 18.0 May 2018
| Kufotokozera | Zotsatira |
| Kutulutsidwa koyambirira kwa zida za Intel Stratix 10. | - |
2.8. 25G Ethernet Intel Stratix 10 FPGA IP User Guide Archives
Mitundu ya IP ndi yofanana ndi mitundu ya Intel Quartus Prime Design Suite mpaka v19.1. Kuchokera ku Intel Quartus Prime Design Suite software version 19.2 kapena mtsogolo, ma IP cores ali ndi dongosolo latsopano la IP.
Ngati mtundu wa IP core sunatchulidwe, chiwongolero cha ogwiritsa ntchito pamtundu wakale wa IP akugwira ntchito.
| Intel Quartus Prime Version | IP Core Version | Wogwiritsa Ntchito |
| 20.3 | 19.4.0 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 20.1 | 19.4.0 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 19.4 | 19.4.0 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 19.3 | 19.3.0 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 19.2 | 19.2.0 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 19.1 | 19.1 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 18.1 | 18.1 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
| 18.0 | 18.0 | 25G Ethernet Intel Stratix 10 FPGA IP User Guide |
2.9. 25G Ethernet Intel Stratix 10 FPGA IP Design Exampndi User Guide Archives
Mitundu ya IP ndi yofanana ndi mitundu ya Intel Quartus Prime Design Suite mpaka v19.1. Kuchokera ku Intel Quartus Prime Design Suite software version 19.2 kapena mtsogolo, ma IP cores ali ndi dongosolo latsopano la IP.
Ngati mtundu wa IP core sunatchulidwe, chiwongolero cha ogwiritsa ntchito pamtundu wakale wa IP akugwira ntchito.
| Intel Quartus Prime Version | IP Core Version | Wogwiritsa Ntchito |
| 19.1 | 19.1 | 25G Ethernet Intel Stratix 10 FPGA IP Design Exampndi User Guide |
| 18.1 | 18.1 | 25G Ethernet Intel Stratix 10 FPGA IP Design Exampndi User Guide |
| 18.0 | 18.0 | 25G Ethernet Intel Stratix 10 FPGA IP Design Exampndi User Guide |
25G Ethernet Intel FPGA IP Release Notes (Zida za Intel Arria 10)
Ngati chikalata chomasulidwa sichikupezeka pamtundu wina wa IP, IP sisintha mu mtunduwo. Kuti mumve zambiri zakusintha kwa IP kutulutsa mpaka v18.1, onani Intel Quartus Prime Design Suite Update Release Notes.
Mitundu ya Intel FPGA IP imafanana ndi mitundu ya Intel Quartus Prime Design Suite mpaka v19.1. Kuyambira mu Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP ili ndi ndondomeko yatsopano yomasulira.
Nambala ya Intel FPGA IP (XYZ) imatha kusintha ndi mtundu uliwonse wa pulogalamu ya Intel Quartus Prime. Kusintha kwa:
- X ikuwonetsa kukonzanso kwakukulu kwa IP. Mukasintha pulogalamu ya Intel Quartus Prime, muyenera kukonzanso IP.
- Y akuwonetsa kuti IP ili ndi zatsopano. Panganinso IP yanu kuti muphatikizepo zatsopanozi.
- Z ikuwonetsa kuti IP imaphatikizapo zosintha zazing'ono. Panganinso IP yanu kuti ikhale ndi zosinthazi.
Zambiri Zogwirizana
- Intel Quartus Prime Design Suite Update Release Notes
- 25G Ethernet Intel Arria® 10 FPGA IP User Guide
- 25G Ethernet Intel Arria® 10 FPGA IP Design Exampndi User Guide
- Errata ya 25G Ethernet Intel FPGA IP mu Knowledge Base
3.1. 25G Efaneti Intel FPGA IP v19.4.1
Gulu 9. v19.4.1 2020.12.14
| Intel Quartus Prime Version | Kufotokozera | Zotsatira |
| 20.4 | Kusintha kwautali pamafelemu a VLAN: • M'matembenuzidwe am'mbuyomu a 25G Ethernet Intel FPGA IP, zolakwika zazikuluzikulu zimatsimikiziridwa pamene zotsatirazi zakwaniritsidwa: 1. VLAN a. Kuzindikira kwa VLAN ndikoyatsidwa. b. IP imatumiza/kulandira mafelemu okhala ndi utali wofikira kutalika kwa chimango cha TX/RX kuphatikiza 1 mpaka 4 octets. 2. SVLAN a. Kuzindikira kwa SVLAN ndikoyatsidwa. b. IP imatumiza/kulandira mafelemu okhala ndi utali wofikira kutalika kwa chimango cha TX/RX kuphatikiza 1 mpaka 8 octets. • Mu mtundu uwu, IP yasinthidwa kuti ikonze izi. |
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| Kusintha mawonekedwe a Avalon-mapu-mapu ofikira mawonekedwe_* kuti mupewe kutha kwa mamapu a Avalon powerenga ma adilesi omwe palibe: • IP imasinthidwa kuti isakhale ngati adilesi yomwe palibe ikupezeka pa mawonekedwe_*. |
3.2. 25G Efaneti Intel FPGA IP v19.4.0
Gulu 10. v19.4.0 2019.12.16
| Intel Quartus Prime Version | Kufotokozera | Zotsatira |
| 19.4 | rx_am_lock kusintha kwamakhalidwe: • M'matembenuzidwe am'mbuyomu a 25G Ethernet Intel FPGA IP, chizindikiro cha rx_am_lock chimachita chimodzimodzi ndi rx_block_lock pamitundu yonse. • Mu mtundu uwu, za RSFEC zoyatsa mitundu yosiyanasiyana ya IP, rx_am_lock tsopano ikunena loko yolumikizira ikakwaniritsidwa. Kwa zosintha zomwe sizili ndi RSFEC, rx_am_lock imagwirabe ntchito ngati rx_block_lock. |
Chizindikiro cha mawonekedwe, rx_am_lock, chimachita mosiyana ndi matembenuzidwe am'mbuyomu amitundu yothandizidwa ndi RSFEC. |
| Kusintha Paketi Yoyambira ya RX MAC: • M'matembenuzidwe am'mbuyomu, RX MAC imangoyang'ana zilembo za START kuti mudziwe chiyambi cha paketi. • Mu mtundu uwu, RX MAC tsopano imayang'ana mapaketi akubwera a Start of Frame Delimiter (SFD), kuwonjezera pa START character mwachisawawa. • Ngati njira yopititsira patsogolo yayatsidwa, MAC imayang'ana zilembo za START zokha kuti zilore kuyambika kwachizolowezi. |
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| Onjezani kaundula watsopano kuti mutsegule zoyambira: • M'marejista a RX MAC, kaundula pa offset 0x50A [4] akhoza kulembedwa kwa 1 kuti athe kuyang'ana koyambirira. Register iyi ndi "osasamala" pomwe mawu oyambira atsegulidwa. |
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3.3. 25G Efaneti Intel FPGA IP v19.1
Gulu 11. v19.1 Epulo 2019
| Kufotokozera | Zotsatira |
| Anapatsanso dzina la Enable Altera Debug Master Endpoint (ADME) kuti Muthandize Native PHY Debug Master Endpoint (NPDME) monga momwe Intel idasinthira mu pulogalamu ya Intel Quartus Prime Pro Edition. Pulogalamu ya Intel Quartus Prime Standard Edition ikugwiritsabe ntchito Enable Altera Debug Master Endpoint (ADME). | - |
3.4. 25G Ethernet IP Core v17.0
Gulu 12. Mtundu wa 17.0 May 2017
| Kufotokozera | Zotsatira |
| Zowonjezera zazithunzi zowerengera zowerengera. • M'marejista a ziwerengero a TX, m'malo mwa kaundula wa CLEAR_TX_STATS pa offset 0x845 ndi regista yatsopano ya CNTR_TX_CONFIG. Regista yatsopano imawonjezera pempho lamthunzi komanso cholakwika chowoneka bwino pang'ono chomwe chimachotsa zolembetsa zonse za TX. Onjezani kaundula watsopano wa CNTR_RX_STATUS pa offset 0x846, zomwe zikuphatikiza cholakwika chaparity komanso mawonekedwe amithunzi. • M'kaundula wa ziwerengero za RX, m'malo mwa kaundula wa CLEAR_RX_STATS pa offset 0x945 ndi regista yatsopano ya CNTR_RX_CONFIG. Regista yatsopanoyi imawonjezera pempho la mthunzi ndi cholakwika chowonekera pang'ono pang'ono. zomwe zimachotsa ziwerengero zonse za TX. Onjezani zolembetsa zatsopano za CNTR_TX_STATUS pa offset 0x946, zomwe zikuphatikiza pang'ono-zolakwika pang'ono ndi kagawo kakang'ono ka pempho lamthunzi. |
Zatsopanozi zimathandizira kudalirika kokhazikika pamawerengedwe owerengera a statistics. Kuti muwerenge kauntala ya ziwerengero, choyamba ikani zopempha zamthunzi za kaundula (RX kapena TX), ndiyeno werengani kuchokera pa chithunzithunzi cha kaundula. Makhalidwe owerengera amasiya kuchulukirachulukira pomwe mawonekedwe amthunzi akugwira ntchito, koma zowerengera zoyambira zikupitilirabe. Mukakhazikitsanso pempho, zowerengera zimayambiranso zikhalidwe zawo zomwe zasonkhanitsidwa. Kuphatikiza apo, minda yatsopano yolembetsa imaphatikizapo mawonekedwe a parityerror ndi ma bits omveka bwino. |
| Zosinthidwa za RS-FEC zolembera zolembera kuti zigwirizane ndi Ndime 108 yomaliza ya IEEE 802.3by kufotokoza. M'mbuyomu mawonekedwe a RS-FEC adagwirizana ndi 25G/50G Consortium Schedule 3, IEEE isanachitike. kutsirizitsa mafotokozedwe. |
RX RS-FEC tsopano imazindikira ndikutseka zolembera zakale ndi zatsopano, koma TX RS-FEC imangopanga mawonekedwe atsopano a IEEE a alignment. |
Zambiri Zogwirizana
- 25G Ethernet IP Core User Guide
- Errata ya 25G Ethernet IP core mu Knowledge Base
3.5. 25G Ethernet IP Core v16.1
Table 13. Version 16.1 October 2016
| Kufotokozera | Zotsatira |
| Kutulutsidwa koyamba mu Intel FPGA IP Library. | - |
Zambiri Zogwirizana
- 25G Ethernet IP Core User Guide
- Errata ya 25G Ethernet IP core mu Knowledge Base
3.6. 25G Ethernet Intel Arria® 10 FPGA IP User Guide Archive
Mitundu ya IP ndi yofanana ndi mitundu ya Intel Quartus Prime Design Suite mpaka v19.1. Kuchokera ku Intel Quartus Prime Design Suite software version 19.2 kapena mtsogolo, ma IP cores ali ndi dongosolo latsopano la IP.
Ngati mtundu wa IP core sunatchulidwe, chiwongolero cha ogwiritsa ntchito pamtundu wakale wa IP akugwira ntchito.
| Intel Quartus Prime Version | Mtundu wa IP | Wogwiritsa Ntchito |
| 20.3 | 19.4.0 | 25G Ethernet Intel Arria® 10 FPGA IP User Guide |
| 19.4 | 19.4.0 | 25G Ethernet Intel Arria 10 FPGA IP User Guide |
| 17.0 | 17.0 | 25G Ethernet Intel Arria 10 FPGA IP User Guide |
3.7. 25G Ethernet Intel Arria 10 FPGA IP Design Exampndi User Kuwongolera Archives
Mitundu ya IP ndi yofanana ndi mitundu ya Intel Quartus Prime Design Suite mpaka v19.1. Kuchokera ku Intel Quartus Prime Design Suite software version 19.2 kapena mtsogolo, ma IP cores ali ndi dongosolo latsopano la IP.
Ngati mtundu wa IP core sunatchulidwe, chiwongolero cha ogwiritsa ntchito pamtundu wakale wa IP akugwira ntchito.
| Intel Quartus Prime Version | IP Core Version | Wogwiritsa Ntchito |
| 16.1 | 16.1 | 25G Ethernet Design Exampndi User Guide |
25G Ethernet Intel® FPGA IP Release Notes
Baibulo Lomasulira
Tumizani Ndemanga
ID: 683067
Mtundu: 2022.09.26
Zolemba / Zothandizira
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Intel 25G Ethernet Intel FPGA IP [pdf] Buku Logwiritsa Ntchito 25G Ethernet Intel FPGA IP, Ethernet Intel FPGA IP, Intel FPGA IP, FPGA IP, IP |